1. Field of Invention
The present invention relates to an apparatus for retiming digital data transmitted at a high speed, and more particularly, to an apparatus for retiming it stably, even though the phase of binary data bits is not related to that of static offset of the retiming clock pulses and there are wander and alignment jitter in the input binary data.
2. Description of the Prior Art
Conventional data retiming devices were designed to provide retiming clock pulses, which have a rising edge in the center of the eye pattern or in the interval of data bits transmitted to retiming parts of the transmission side and the receiving side from the source clock generation part, as shown in FIGS. 1A and 1B. The timing of data transmitted in parallel or in serial is predictable at the retiming part of the receiving side due to the relatively slow speed of the data bits. However, it is more difficult to predict phases between receiving data and clock pulse at the retiming part of the receiving side when the interval of data bits is reduced due to the increased speed of data bits. Accordingly, a conventional device for retiming data transmitted at a high speed can not meet the hold time and the setup time of a D-type flip-flop, and metastability occurs. Metastability is also generated due to environmental factors, even though the transmission distance is relatively short and the size of alignment jitter is small. These matters make stable retiming impossible.
To solve the above problems, a variety of methods using the concept of bit synchronization of transmission have been provided, in which the transmission side transmits only data and the receiving side generates retiming clock pulses from the received data through a non-linear process or performs data retiming by generating retiming clock pulses with a voltage control oscillator. Representative references are C. P. Summers (U.S. Pat. No. 4,422,176), M. Belkin (U.S. Pat. No. 4,400,667), and C. R. Hogge (U.S. Pat. No. 4,535,459). In addition, an application retiming device (AMCC 20P025, retiming chip Applied by Micro Corp.) was invented. However, these methods have a bit synchronization device with a complicated structure. While the devises perform stable data retiming for transmitting data at a high speed, they are too complex and non-economical to use for a data link which is transmitted in parallel because integration is difficult due to use of analog parts, such as a voltage control oscillator and a low pass filter.
Additionally, digital bit synchronization devices perform received data retiming by using a clock pulse with a cycle of 1/16 times data unit bit interval transmitted, such as M. Tanaka (U.S. Pat. No. 4,385,395). Tanaka has the advantage of not using an analog low-pass filter, but has the disadvantage of not being suitable for performing data retiming at a high speed, since that requires a more stable clock pulse than the data bits at the high speed.
On the other hand, Kwan (U.S. Pat. No. 5,036,529) discloses a retiming device which adapts received data to the retiming clock pulse by delaying the data with active delay elements. This device has the advantage of performing a relatively stable retiming function by using a clock pulse with the same period as the data unit bit interval, but the device can not perform stable retiming functions when the static offset phase between the data and the clock pulse reaches the limitation of the delay element alignment jitter.